Integrated circuits (IC) are known to include a package that houses at least one die which is coupled to a plurality of pads, or pins. The size of the package, and hence the size of the IC, depends on the size of the die or dies and the number of required pins. In turn, the die size depends on the complexity of the circuit(s) deposited thereon and the size of the gate oxide layer. The less complex the circuit and/or the smaller the gate oxide layer, the smaller the resulting die.
As advances in IC manufacturing techniques continue to occur, the size of the gate oxide layer continues to decrease. For example, current state of the art gate oxide layer size is approximately 0.35 micron (.mu.), where a typical gate oxide layer size is 0.60.mu.. As the size of the gate oxide layer decreases, more complex circuit may be deposited on a single, smaller, die. Thus, an IC manufacturer may produce smaller, more complex, integrated circuits using smaller gate oxide layers. This, however, comes with a tradeoff of lower yields (more dies fail to pass testing). Thus, an IC manufacturer will balance circuit complexity, die size, and desired yield.
For example, if an IC manufacturer produces a video graphics controller integrated circuit using 0.6.mu. gate oxide layer technology, the IC manufacture may expect a yield of approximately eighty percent, while a 2 Mbyte RAM, using the same 0.6.mu., may have a yield of approximately eighty-five percent. If the IC manufacturer were to combine these two circuits (i.e., the video graphics controller and the 2 Mbyte RAM) on to a single die using the same gate oxide layer size, the expected yield would be sixty eight percent (0.8.sup.* 0.85). The expected yield would be even lower if the IC manufacturer used a smaller gate oxide layer size.
Because of the above mentioned decrease in yield, IC manufacturers are reluctant to place two such separate circuits on a single die. In addition to the lower yields, testing of such a die requires more time because of the additional circuitry, thereby further decreasing the effective yield. The effective yield is decreased even if one of the separate circuits was completely functional (i.e., passed testing) because the overall die did not pass. Thus, when such a partial functioning die is detected, it is scrapped as if the entire die failed. As one can image, such scrapping of dies is costly to the IC manufacturer and to the subsequent IC consumers.
Therefore, a need exists for an method and apparatus for reconfiguring an integrated circuit based on testing results.